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Data Sheet, Rev. 1.2, April 2004
HYB25L256160AF HYE25L256160AF
256MBit Mobi le- RAM Mobile-RAM Commercial Temperature Range E x t en d e d T e m p e r a t u r e R a n g e
M e m or y P r o du c t s
Never
stop
thinking.
The information in this document is subject to change without notice. Edition 04-2004 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet, Rev. 1.2, April 2004
HYB25L256160AF HYE25L256160AF
256MBit Mobi le- RAM Mobile-RAM Commercial Temperature Range E x t en d e d T e m p e r a t u r e R a n g e
M e m or y P r o du c t s
Never
stop
thinking.
HYB25L256160AF HYE25L256160AF Revision History: Previous Revision: Page all all Rev. 1.2 Rev. 1.1 04-2004 2003-09
Subjects (major changes since last revision) Add Commercial Temperature Range Add (Green Product) for commercial and extended temperature range
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
Template: mp_a4_v2.3_2004-01-14.fm
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Table of Contents 1 1.1 1.2 2 3 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.3 3.3.1 3.3.2 3.4 3.5 4 4.1 4.2 4.3 5 6 Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Compensated Self Refresh with On-Chip Temperature Sensor . . . . . . . . . . . . . . . . Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 13 14 14 14 15 15 15 16 20 21 21 22 24
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Data Sheet
5
Rev. 1.2, 04-2004
256MBit Mobile-RAM Mobile-RAM
HYB25L256160AF HYE25L256160AF
1
1.1
* * * * * * * * * * * * * * * * * * * * * *
Overview
Features
16 Mbits x 16 organisation Fully synchronous to positive clock edge Four internal banks for concurrent operation Data mask (DM) for byte control with write and read data Programmable CAS latency: 2 or 3 Programmable burst length: 1, 2, 4, 8, or full page Programmable wrap sequence: sequential or interleaved Random column address every clock cycle (1-N rule) Deep power down mode Extended mode register for Mobile-RAM features Temperature compensated self refresh with on-die temperature sensor Partial array self refresh Power down and clock suspend mode Automatic and controlled precharge command Auto refresh mode (CBR) 8192 refresh cycles / 64 ms Self-refresh with programmble refresh period Programmable power reduction feature by partial array activation during self-refresh VDDQ = 1.8V or 2.5 V or 3.3 V VDD = 2.5 V or 3.3 V P-TFBGA-54 package 9-by-6-ball array with 3 depopulated rows (12 x 8 mm2) Operating temperature range: commercial (0 C to +70 C) extended (-25 C to +85 C) Performance 1) -7.5 @CL3 @CL3 @CL3 @CL2 @CL2 Unit MHz ns ns ns ns
Table 1
Part Number Speed Code max. Clock Frequency min. Clock Period min. Access Time from Clock min. Clock Period min. Access Time from Clock
fCK3 tCK3 tAC3 tCK2 tAC2
133 7.5 6.0 9.5 6.0
1) for VDDQ = 2.5 V or 3.3 V; see Table 10 for VDDQ dependent performance
1.2
Description
The 256MBit Mobile-RAM is a new generation of low power, four bank synchronous DRAM organized as 4 banks x 4 Mbit x 16 with additional features for mobile applications. The synchronous Mobile-RAM achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The device adds new features to the industry standards set for synchronous DRAM products. Parts of the memory array can be selected for Self-Refresh and the refresh period during Self-Refresh is programmable in 4 steps Data Sheet 6 Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Overview
which drastically reduces the self refresh current, depending on the case temperature of the components in the system application. In addition a "Deep Power Down Mode" is available. Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. The Mobile-RAM is housed in a FBGA "chip-size" package. The Mobile-RAM is available in the commercial (0 C TC 70 C) and extended (-25 C to +85 C) temperature range. Table 2 Ordering Information Function Code PC133-333-522 PC133-333-522 Case Temperature Range commercial (0 C TC 70 C) extended (-25 C to +85 C) Package P-TFBGA-54 P-TFBGA-54
Part Number1) HYB25L256160AF-7.5 HYE25L256160AF-7.5
1) HYB/E: designator for memory components for commercial /extended temperature range 25L: Mobile-RAM at VDD = 2.5 V 256: 256-Mbit density 160: Product variation x16 A: Die revision A F: Lead & Halogen free -7.5: speed grade - see Table 1
Data Sheet
7
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Pin Configuration
2
Pin Configuration
1 VSS DQ14 DQ12 DQ10 DQ8 UDQM A12 A8 VSS
2 DQ15 DQ13 DQ11 DQ9 NC CLK A11 A7 A5
3 VSSQ VDDQ VSSQ VDDQ VSS CKE A9 A6 A4 A B C D E F G H J
7 VDDQ VSSQ VDDQ VSSQ VDD CAS BA0 A0 A3
8 DQ0 DQ2 DQ4 DQ6 LDQM RAS BA1 A1 A2
9 VDD DQ1 DQ3 DQ5 DQ7 WE CS A10/AP VDD
< Top-view >
Figure 1
Pin Configuration P-TFBGA-54 (16 Mb x 16)
Data Sheet
8
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Pin Configuration
Table 3 F2 CLK Input/Output Signals Polarity Function Positive Clock Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Active High Clock Enable CKE activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode, Suspend mode, or the Self Refresh mode. Chip Select CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Command Inputs Sampled at the rising edge of the clock, RAS, CAS, and WE (along with CS) define the command to be executed by the SDRAM. Bank Address Inputs BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determine if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs During a Bank Activate command cycle, A12 - A0 define the row address (RA12 - RA0) when sampled at the rising clock edge. During a Read or Write command cycle, A8-A0 define the column address (CA8 - CA0) when sampled at the rising clock edge. In addition to the column address, A10/AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA1, BA0 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA1 and BA0 to control which bank(s) to precharge. If AP is high, all four banks will be precharged regardless of the state of BA0 and BA1. If AP is low, then BA1 and BA0 are used to define which bank to precharge. Input
Pin Symbol Type
F3
CKE
Input
G9 CS
Input
Active Low
F8 F7 F9
RAS CAS WE
Input
Active Low
G8 BA1 G7 BA0
Input
Active High
G1 A12 G2 A11 H9 A10/AP G3 A9 H1 A8 H2 A7 H3 A6 J2 J3 J7 J8 A5 A4 A3 A2
Input
Active High
H8 A1 H7 A0
Data Sheet
9
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Pin Configuration
Table 3 A2 DQ15 B1 DQ14 B2 DQ13 C1 DQ12 C2 DQ11 D1 DQ10 D2 DQ9 E1 DQ8 E9 DQ7 D8 DQ6 D9 DQ5 C8 DQ4 C9 DQ3 B8 DQ2 B9 DQ1 A8 DQ0 F1 UDQM Input E8 LDQM Active High Data Input/Output Mask UDQM and LDQM are output disable signals during read mode and input mask signals for write data. In Read mode, U/LDQM have a latency of two clock cycles and control the output buffers like low active output enable signals. In Write mode, U/LDQM have a latency of zero and operate as a word mask by allowing input data to be written if it is low but blocks the write operation if the respective DQM is high. UDQM controls the upper byte and LDQM controls the lower byte. Not Connected No internal electrical connection is present. DQ Power Supply Input/Output Signals (cont'd) Polarity Function Data Input/Output Data bus operates in the same manner as on conventional DRAMs. Input/ Active Output High
Pin Symbol Type
E2 NC A7, VDDQ B3, C7, D3 A3 VSSQ B7 C3 D7 A9 VDD E4 J9 A1 VSS E3 J1
-
-
Supply -
Supply -
DQ Ground
Supply -
Power Supply
Supply -
Ground
Data Sheet
10
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Pin Configuration
Column Addresses A0 - A8, AP, BA0, BA1
Row Addresses A0 - A12, BA0, BA1
Column Address Counter
Column Address Buffer
Row Address Buffer
Refresh Counter
Row Decoder
Row Decoder
Row Decoder
Row Decoder
Column Decoder Sense amplifier & I(O) Bus
Column Decoder Sense amplifier & I(O) Bus
Column Decoder Sense amplifier & I(O) Bus
Memory Array
Memory Array
Memory Array
Column Decoder Sense amplifier & I(O) Bus
Memory Array
Bank 0 8192 x 512 x 16 Bit
Bank 1 8192 x 512 x 16 Bit
Bank 2 8192 x 512 x 16 Bit
Bank 3 8192 x 512 x 16 Bit
Input Buffer
Output Buffer
Control Logic & Timing Generator
DQ0 - DQ15
Figure 2 Note:
Block Diagram (16 Mbit x 16, 13 / 9 / 2 Addressing)
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 2. DQM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ signals.
Data Sheet
11
CLK CKE CS RAS CAS WE UDQM LDQM
SPB04124_256M
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Functional Description
3
Functional Description
The 256MBit Mobile-RAM is a new generation of low power, four bank synchronous DRAM organized as 4 banks x 4 Mbit x 16 with additional features for mobile applications. The synchronous Mobile-RAM achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The device adds new features to the industry standards set for synchronous DRAM products. Parts of the memory array can be selected for Self-Refresh and the refresh period during Self-Refresh is programmable in 4 steps which drastically reduces the self refresh current, depending on the case temperature of the components in the system application. In addition a "Deep Power Down Mode" is available. Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Prior to normal operation, the 256MBit Mobile-RAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
3.1
Initialization
The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the 256MBit Mobile-RAM must be powered up and initialized in a predefined manner. VDD must be applied before or at the same time as VDDQ to the specified voltage when the input signals are held in the "NOP" or "DESELECT" state. The power on voltage must not exceed VDD + 0.3 V on any of the input pins or VDDQ supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 s is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of two Auto Refresh cycles (CBR) are also required. These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.
3.2
Mode Register Definition
The Mode Register designates the operation mode at the read or write cycle. This register is divided into four fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to program the column access sequence in a burst cycle (interleaved or sequential), and a CAS Latency Field to set the access time at clock cycle, an The mode set operation must be done before any activate command after the initial power up. Any content of the mode register can be altered by re-executing the mode set command. All banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table. BA0 and BA1 have to be set to "0" to enter the Mode Register.
Data Sheet
12
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Functional Description
MR Mode Register Definition
BA1 0 BA0 0 A12 A11 A10 A9
(BA[1:0] = 00B)
A8 A7 A6 A5 CL w A4 A3 BT w A2 A1 BL w A0
MODE w
reg. addr
Field BL
Bits [2:0]
Type w
Description Burst Length Number of sequential bits per DQ related to one read/write command; see Chapter 3.2.1. Note: All other bit combinations are RESERVED. 000 001 010 011 111 1 2 4 8 full page (sequential burst type only)
BT
3
w
Burst Type See Table 4 for internal address sequence of low order address bits; see Chapter 3.2.2. 0 Sequential 1 Interleaved CAS Latency Number of full clocks from read command to first data valid window; see Chapter 3.2.3. Note: All other bit combinations are RESERVED. 010 2 011 3
CL
[6:4]
w
MODE [12:7] w
Operating Mode See Chapter 3.2.4. Note: All other bit combinations are RESERVED. 000000 000100 Burst Read/Burst Write Burst Read/Single Write
3.2.1
Burst Length
Read and write accesses to the 256MBit Mobile-RAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by Ai-A1 when the burst length is set to two, by Ai-A2 when the burst length is set to four and by Ai-A3 when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies always to Read bursts and depending on A9 in Operating Mode also on Write bursts.
Data Sheet
13
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Functional Description
3.2.2
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 4. Table 4 Burst Length 2 4 0 0 1 1 8 0 0 0 0 1 1 1 1 Note: 1. For a burst length of two, Ai-A1 selects the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, Ai-A2 selects the four-data-element block; A1-A0 selects the first access within the block. 3. For a burst length of eight, Ai-A3 selects the eight-data- element block; A2-A0 selects the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 0 0 1 1 0 0 1 1 Burst Definition Starting Column Address A2 A1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
3.2.3
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2 and 3 clocks. If a Read command is registered at rising clock edge n, and the latency is m clocks, the data is available nominally coincident with rising clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
3.2.4
Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A12-A7 set to zero, and bits A6-A0 set to the desired values. Burst Length for Write bursts is fixed to one by issuing a Mode Register Set command with bits A12-A10 and A8-A7 each set to zero, bit A9 set to one, and bits A0-A6 set to the desired values. All other combinations of values for A12-A7 are reserved for future use and/or test modes. Test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result.
Data Sheet
14
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Functional Description
3.3
Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register. These additional functions are unique to Mobile RAMs and includes a refresh period field (TCSR) for Temperature Compensated Self Rrefresh and a Partial Array Self Refresh field (PASR). The Extended Mode Register is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 1) and retains the stored information until it is programmed again or the device looses power. The Extended mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either these requirements result in unspecified operation. Unused bit A12 to A5 have to be programmed to "0".
3.3.1
Partial Array Self Refresh
The PASR field is a power saving feature specific to Mobile-RAMs and is used to specify whether only one quarter or half of bank 0, one bank (bank 0), two banks (banks 0 + 1) or all four banks (default) of the SDRAM array are enabled for Self Refresh. Disabled banks will not be refreshed in Self Refresh mode and written data will get lost after a period defined by tREF.
3.3.2
Temperature Compensated Self Refresh with On-Chip Temperature Sensor
DRAM devices store data as electrical charge in tiny capacitors that require a periodic refresh in order to retain the stored information. This refresh requirment heavily depends on the die temperatur: high temperature corresponds to short refresh period, and low temperature to long refresh period. The Mobile-RAM is equipped with an on-chip temperature sensor which continuously monitors the current die temperature and adjusts the refresh period in self refresh mode accordingly. By default the on-chip temperature sensor is enabled (TCSR = 00, see Table "EMR" on Page 15); the other three TCSR settings use defined temperature values to adjust the self refresh period to with the on-chip temperature sensor being disabled. EMR Extended Mode Register Definition
BA1 1 BA0 0 A12 A11 A10 A9
(BA[1:0] = 10B)
A8 A7 A6 A5 A4 A3 A2 A1 PASR w A0
MODE w
TCSR w
reg. addr
Field PASR
Bits [2:0]
Type w
Description1) Partial Array Self Refresh See Chapter 3.3.1 000 banks to be self refreshed: all 4 of 4 001 banks to be self refreshed: 2 of 4, BA[1:0] = 00B or 01B 010 banks to be self refreshed: 1 of 4, BA[1:0] = 00B 101 banks to be self refreshed: 0.5 of 4, BA[1:0] = 00B & RA12 = 0B 110 banks to be self refreshed: 0.25 of 4, BA[1:0] = 00B & RA[12:11] = 00B Temperature Compensated Self Refresh See Chapter 3.3.2. 00 on-chip temperature sensor enabled 01 Maximum case temperature: 45C, on-chip temperature sensor disabled 10 Maximum case temperature: 15C, on-chip temperature sensor disabled 11 Maximum case temperature: 85C, on-chip temperature sensor disabled Operating Mode 00h Normal operation
TCSR
[4:3]
w
MODE
[12:5]
w
1) All other bit combinations are RESERVED.
Data Sheet
15
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Functional Description
3.4
Commands
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands. Table 5 Operation Bank Active Bank Precharge Precharge All Write Write with Autoprecharge Read Read with Autoprecharge Mode Register Set No Operation Burst Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit Clock Suspend Entry Clock Suspend Exit Operation Definition1) Device State Idle3) Any Any Active Active Idle Any Active Any Idle Idle Idle (Self Refresh) Active Active
4) 3) 3) 3) 3)
CKE CKE DQM BA1 AP= Addr CS RAS CAS WE n-12) n2) BA0 A10 H H H H H H H H H H H H H L H L H L H H H
5)
X X X X X X X X X X X H L H L H L H X X L H
X X X X X X X X X X X X X X X X X X L H X X
V V X V V V V V X X X X X X X X X X X X X X
V L H L H L H V X X X X X X X X X X X X X X
V X X V V V V V X X X X X X X X X X X X X X
L L L L L L L L L L H L L H L X X H L H L X X L X
L L L H H H H L H H X L L X H X X X H X H X X H X
H H H L L L L L H H X L L X H X X X H X H X X H X
H L L L L H H L H L X H H X X X X X H X L X X L X
Active Active
Power Down Entry Idle (Precharge or active standby) Active4) Power Down Exit Data Write/Output Enable Data Write/Output Disable Deep Power Down Entry Deep Power Down Exit Any (Power Down) Active Active Idle Deep Power Down
L
1) V = Valid, x = Don't Care, L = Low Level, H = High Level. 2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3) This is the state of the banks designated by BA0, BA1 signals.
4) Power Down Mode can not be entered during a burst cycle. When this command is asserted during a burst cycle the device enters Clock Suspend Mode.
5) After Deep Power Down mode exit a full new initialisation of the memory device is mandatory.
Data Sheet
16
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Functional Description
Deselect The Deselect function prevents new commands from being executed by the 256MBit Mobile-RAM. Operations already in progress are not affected. No Operation (NOP) The No Operation (NOP) command is used to perform a NOP to a 256MBit Mobile-RAM. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Mode Register Set The mode registers are loaded via inputs A12-A0, BA1 and BA0. See mode register descriptions in Chapter 3.2. The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met. Active The Active command is used to open (or activate) a row in a particular bank for a subsequent access. This is called the start of a RAS cycle and occures when RAS is low and both CAS and WE are high at the positive edge of the clock. The value on the BA1 and BA0 inputs selects the bank, and the address provided on inputs A12-A0 selects the row. This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before opening a different row in the same bank. Read and Write A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 133 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, which is one of 1, 2, 4, 8 and full page. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is `2', then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O organisation and column addressing. Full page burst operation does not self terminate once the burst length has been reached. In other words, unlike burst length of 2, 4 and 8, full page burst continues until it is terminated using another command. Similar to the page mode of conventional DRAM's, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycle is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. Once two or more banks are activated, column to column interleave operation can be performed between different pages. When the partial array activation is set, data will get lost when self-refresh is used in all non activated banks. The Read command is used to initiate a burst read access to an active (open) row. The value on the BA1 and BA0 inputs selects the bank, and the address provided on inputs A9-A0 for x16 selects the starting column location. The value on input A10/AP determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open for subsequent accesses.
Data Sheet
17
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Functional Description
The Write command is used to initiate a burst write access to an active (open) row. The value on the BA1 and BA0 inputs selects the bank, and the address provided on inputs A9-A0 for x16 selects the starting column location. The value on input A10/AP determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered low, the corresponding data is written to memory; if the DQM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column location. Precharge The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge command is issued. When RAS and WE are low and CAS is high at a clock edge, it triggers the precharge operation. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care" (see Table 6). Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write commands being issued to that bank. A precharge command is treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging. The precharge command can be imposed one clock before the last data out for CAS latency = 2 and two clocks before the last data out for CAS latency = 3. Writes require a time delay tWR from the last data out to apply the precharge command. Table 6 A10 0 0 0 0 1 Bank Selection by Address Bits with Precharge BA0 0 0 1 1 x BA1 0 1 0 1 x Bank 0 Bank 1 Bank 2 Bank 3 all Banks
Auto Precharge Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. This is accomplished by using A10/AP to enable Auto Precharge in conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read or Write command is automatically performed upon completion of the Read or Write burst. Auto Precharge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge (tRP) is completed. This is determined as if an explicit Precharge command was issued at the earliest possible time. The 256MBit Mobile-RAM automatically enters the precharge operation after tWR (Write recovery time) following the last data in. Burst Terminate Once a burst read or write operation has been initiated, there are several methods used to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, using a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. Data Sheet 18 Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Functional Description
Auto Refresh Auto Refresh is used during normal operation of the 256MBit Mobile-RAM and is analogous to CAS Before RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required. All banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses. This makes the address bits "Don't Care" during an Auto Refresh command. The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock edge. The mode restores word line after the refresh and no external precharge command is necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. In Auto-Refresh mode all banks are refreshed, independendly of the fact that the partial array self-refresh has been set or not. Self Refresh The chip has an on-chip timer that is used when the Self Refresh mode is entered. The self-refresh command is asserted with RAS, CAS, and CKE low and WE high at a clock edge. All external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to any access command. The use of self refresh mode introduces the possibility that an iternally timed event can be missed when CKE is raised for exit from self refresh mode. Upon exit from self refresh an extra auto refresh command is recommended. Low Power SDRAMs have the possibility to program the refresh period of the on-chip timer with the use of an appropriate extended MRS command, depending on the maximum operation case temperature in the application. In partial array self refresh mode only the selected banks will be refreshed. Data written to the non activated banks will get lost after a period defined by tref. DQM Function DQM has two functions for data I/O read and write operations. During reads, when it turns to "high" at a clock edge, data outputs are disabled and become high impedance after two clock periods (DQM Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks). Suspend Mode During normal access, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend Latency tCSL). Power Down In order to reduce standby power consumption, a power down mode is available. All banks must be precharged before the Mobile-RAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all receiver circuits except for CLK and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can't remain in Power Down mode longer than the Refresh period (tREF) of the device. Exit from this mode is performed by taking CKE "high". One clock delay is required for power down mode entry and exit. Deep Power Down Mode The Deep Power Down Mode is an unique function on Mobile RAMs with very low standby currents. All internal voltage generators inside the Mobile RAMs are stopped and all memory data is lost in this mode. To enter the Deep Power Down mode all banks must be precharged.
Data Sheet
19
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Functional Description
3.5
Simplified State Diagram
Power applied
Power On
DPDSX
Deep Power Down
Precharge All PREALL
DPDS REFSX REFS
Self Refresh
Mode Register Set
MRS
Idle
REFA CKEL CKEH
Auto Refresh
Active Power Down
CKEH CKEL
T BS W
ACT
Precharge Power Down
Row Active
TE RI
BS T RE AD
WRITEA
Clock Suspend WRITE
READA READ
CKEL CKEH
WRITE
WRITE
READ
CKEL CKEH
Clock Suspend READ
WRITEA
WRITEA PRE PRE
READ A PRE
READA
Clock Suspend WRITEA
CKEL CKEH PRE
WRITE A
READ A
CKEL CKEH
Clock Suspend READA
Precharge Automatic Sequence Command Sequence
PREALL = Precharge All Banks REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh DPDS = Enter Deep Power Down DPDSX = Exit Deep Power Down
CKEL = Enter Power Down CKEH = Exit Power Down READ = Read w/o Auto Precharge READA = Read with Auto Precharge WRITE = Write w/o Auto Precharge WRITEA = Write with Auto Precharge
ACT = Active PRE = Precharge BST = Burst Terminate MRS = Mode Register Set
Figure 3 Data Sheet
Simplified State Diagram 20 Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Electrical Characteristics
4
4.1
Table 7 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol min. Values typ. -- -- -- -- -- -- -- 50 max. -1.0 -1.0 -1.0 -1.0 -25 -55 -- -- Unit Note/ Test Condition -- -- -- -- -- -- -- --
Voltage on I/O pins relative to VSS Voltage on I/O pins relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating Case Temperature (extended) Storage Temperature (Plastic) Power Dissipation Short Circuit Output Current
VIN, VOUT VIN, VOUT VDD VDDQ TCASE TSTG PD IOUT
VDD + 0.5 V
+4.6 +4.6 +4.6 +85 +150 0.7 -- V V V C C W mA
Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Table 8 Parameter Supply Voltage I/O Supply Voltage Supply Voltage I/O Supply Voltage Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Output High (Logic 1) Voltage Output Low (Logic 0) Voltage Input Leakage Current Output Leakage Current
2) VDDQ < VDD + 0.3 V 3) All voltages referenced to VSS 4)
Recommended Operating Conditions and DC Characteristics1) Symbol min. Values max. +3.6 +3.6 0 0 V V V V V V V V A A --
2)
Unit Note/ Test Condition
VDD VDDQ VSS VSSQ VIH VIL VOH VOL IIL IOZ
+2.3 +1.65 0 0 0.8 x VDDQ -0.3 -- -5 -5
-- --
3)4) 3)4)
VDDQ + 0.3
+0.3 +0.2 +5 +5
VDDQ - 0.2 --
IOH = -0.1 mA IOH = +0.1 mA Any input 0 V VIN VDD; all other pins not under test VIN = 0 V DQ is disabled; 0 V VOUT VDDQ
1) 0 C TC 70 C (comm.) and -25 C TCASE +85 C
VIH may overshoot to VDDQ + 2.0 V for pulse width of < 4 ns. VIL may undershoot to - 2.0 V for pulse width < 4 ns.
Pulse width measured at 50% points with amplitude measured peak to DC reference
Data Sheet
21
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Electrical Characteristics
Table 9 Parameter
Input and Output Capacitances Symbol min. Values typ. - - - max. 3.5 3.8 5.0 pF pF pF - - 4.0 Unit Note/ Test Condition
1) 1)
1)
Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQ
CI1 CI2 CIO
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V 0.2 V, f = 1 MHz, TCASE = 25 C, VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
4.2
Table 10 Parameter Clock
Timing Characteristics
AC Timing Characteristics1)2) Symbol min. -7.5 max. 7.5 6 5.4 7.5 6 - - - - - 133 125 105 - - - - - 7.5 - - 100000 - - - ns ns ns ns ns ns ns ns ns ns Unit Note/ Test Condition
DQ output access time from CLK
tAC3
- - -
tAC2
CK high-level width CK low-level width Clock cycle time
- - 2.5 2.5 7.5 8 9.5 - - - 1.5 0.8 1.5 0.8 2 0 19 19 45 67 15 1
VDDQ < 2.3 V 3)4)5)8) VDDQ 2.3 V 3)4)5)8) VDDQ 3.0 V 3)4)5)8) VDDQ < 2.3 V 3)4)5)8) VDDQ 2.3 V 3)4)5)8)
- -
tCH tCL tCK3 tCK2 fCK3 fCK2
VDDQ 2.3 V 3) VDDQ < 2.3 V 3)
3)
Clock frequency
MHz VDDQ 2.3 V 3) MHz VDDQ < 2.3 V 3) MHz ns ns ns ns
3)
Setup and Hold Times Input setup time Input hold time CKE setup time CKE hold time Mode register setup time Power down moder entry time Common Parameters Active to Read or Write delay Precharge command period Active to Precharge command Active bank A to Active bank A period Active bank A to Active bank B delay CAS to CAS command delay
tIS tIH tCKS tCKH tRSC tSB tRCD tRP tRAS tRC tRRD tCCD
6) 6) 6) 6)
tCK
ns ns ns ns ns ns
- -
7) 7) 7) 7) 7)
tCK
-
Data Sheet
22
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Electrical Characteristics
Table 10 Parameter Refresh Cycle Refresh period Self refresh exit time Read Cycle Data output hold time Data output from high to low impedance Data output from low to high impedance DQM data output disable latency Write Cycle Write recovery time DQM write data mask latency AC Timing Characteristics1)2) (cont'd) Symbol min. -7.5 max. 64 - - - 7 2 - - ms - -
4)7)8)
Unit Note/ Test Condition
tREF tSREX tOH tLZ tHZ tDQZ tWR tDQW
- 1 3 1 3 - 14 0
tCK
ns ns ns
- - -
9)
tCK
ns
tCK
-
1) 0 C TC 70 C (comm.) and -25 C TCASE +85 C; recommended operating conditions unless otherwise noted 2) For proper power-up see the operation section of this data sheet. 3) Symbol index 2 and 3 refer to CL = 2 and CL = 3. 4) AC timing tests are referenced to the 0.9 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit (details will be defined later). Specified tAC and tOH parameters are measured with a 30 pF only, without any resistive termination and with a input signal of 1V/ns edge rate (see Figure 4). 5) If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter. 6) If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter. 7) These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) 8) Access time from clock tAC is 4.6 ns for -7.5 components with no termination and 0 pF load, Data out hold time tOH is 1.8 ns for -7.5 components with no termination and 0 pF load. 9) The write recovery time of tWR = 14 ns allows the use of one clock cycle for the write recovery time when the memory operation frequency is equal or less than 72MHz. For all memory operation frequencies higher than 72MHz two clock cycles for tWR are mandatory. INFINEON recommends to use two clock cylces for the write recovery time in all applications.
I/O 30 pF
Figure 4
Measurement Conditions for tAC and tOH
Data Sheet
23
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Electrical Characteristics
4.3
Table 11 Parameter
Current Specification
IDD Specification and Conditions1)2)
Symbol typ. -7.5 max. 65 0.6 20 3.5 25 80 155 mA mA mA mA mA mA mA A A -- -- -- -- -- -- -- Unit Note/ Test Condition
Operating current Single bank access cycles Precharge standby current Power down mode Precharge standby current Non power down mode Non operating current Active state of 1 upto 4 banks, power down Non operating current Active state of 1 upto 4 banks, non power down Burst operating current Read command cycling Auto refresh current Auto refresh command cycling Self refresh current Deep power down mode current
IDD1 IDD2P IDD2N IDD3P IDD3N IDD4 IDD5 IDD6 IDD7
tRC = tRC,MIN 3)
CS = VIH,MIN, CKE VIL,MAX 3) CS = VIH,MIN, CKE VIH,MIN 3) CS = VIH,MIN, CKE VIL,MAX 3) CS = VIH,MIN, CKE VIH,MIN 3)
3)4)
tRC = tRC,MIN tCK =infinity,
CKE = 0.2 V
see Table 12 -- 5
1) 0 C TC 70 C (comm.) and -25 C TCASE +85 C; recommended operating conditions unless otherwise noted 2) For proper power-up see the operation section of this data sheet. 3) These parameters depend on the frequency. These values are measured at 133MHz for -7.5 and at 100MHz for -8 parts. Input signals are changed once during tCK. If the devices are operating at a frequency less than the maximum operation frequency, these current values are reduced. 4) These parameters are measured with continuous data stream during read access and all DQs toggling. CL = 3 and BL = 4 is used and the VDDQ current is excluded.
Data Sheet
24
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Electrical Characteristics IDD6 Programmable Self Refresh Current1)2)
Symbol -8 max. Self refresh current Self refresh mode, full array activations = all banks t.b.d. 250 475 725 Self refresh current IDD6 Self refresh mode, half array activations = bank 0 + 1 t.b.d. 150 250 450 Self refresh current IDD6 Self refresh mode, quarter array activations = bank 0 t.b.d. 100 150 275 Unit TCASE TCSR A A A A A A A A A A A A
3)
Table 12 Parameter
Note/ Test Condition
IDD6
max. 15C max. 45C max. 70C max. 85C max. 15C max. 45C max. 70C max. 85C max. 15C max. 45C max. 70C max. 85C
tCK =infinity,
CKE = 0.2 V 4)
tCK =infinity,
CKE = 0.2 V 4)
tCK =infinity,
CKE = 0.2 V 4)
1) Recommended operating conditions unless otherwise noted 2) For proper power-up see the operation section of this data sheet. 3) Extended Mode Register A4-A3, see "Temperature Compensated Self Refresh with On-Chip Temperature Sensor" on Page 15 4) Target values to be verified on final product and may change.
Data Sheet
25
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
5
Timing Diagrams
Figure 5 Bank Activate Command Cycle Figure 6 Burst Read Operation Figure 7 Read Interrupted by a Read Read to Write Interval - Figure 8 Read to Write Interval - Figure 9 Minimum Read to Write Interval - Figure 10 Non-Minimum Read to Write Interval Figure 11 Burst Write Operation Write and Read Interrupt - Figure 12 Write Interrupted by a Write - Figure 13 Write Interrupted by Read Burst Write & Read with Auto-Precharge - Figure 14 Burst Write with Auto-Precharge - Figure 15 Burst Read with Auto-Precharge AC- Parameters - Figure 16 AC Parameters for a Write Timing - Figure 17 AC Parameters for a Read Timing Figure 18 Mode Register Set Figure 19 Power on Sequence and Auto Refresh (CBR) Clock Suspension (using CKE) - - - - Figure 20 Clock Suspension During Burst Read CAS Latency = 2 Figure 21 Clock Suspension During Burst Read CAS Latency = 3 Figure 22 Clock Suspension During Burst Write CAS Latency = 2 Figure 23 Clock Suspension During Burst Write CAS Latency = 3
Figure 24 Power Down Mode and Clock Suspend Figure 25 Self Refresh (Entry and Exit) Figure 26 Auto Refresh (CBR) Random Column Read ( Page within same Bank) - Figure 27 CAS Latency = 2 - Figure 28 CAS Latency = 3 Random Column Write ( Page within same Bank) - Figure 29 CAS Latency = 2 - Figure 30 CAS Latency = 3 Random Row Read (Interleaving Banks) with Precharge - Figure 31 CAS Latency = 2 - Figure 32 CAS Latency = 3 Random Row Write (Interleaving Banks) with Precharge - Figure 33 CAS Latency = 2 - Figure 34 CAS Latency = 3 Precharge Termination of a Burst - Figure 35 CAS Latency = 2 Deep Power Down Mode - Figure 36 Deep Power Down Mode Entry - Figure 37 Deep Power Down Mode Exit
Data Sheet
26
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
(CAS latency = 3)
T0 CLK T1 T T T T T
Address
Bank B Row Addr.
Bank B Col. Addr.
Bank A Row Addr.
Bank B Row Addr.
t RCD Command
Bank B Activate
t RRD NOP
Write B with Auto Precharge
NOP
Bank A Activate
NOP
Bank B Activate
t RC "H" or "L"
SPT03784
Figure 5
Bank Activate Command Cycle
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Read A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's
Figure 6 Burst Read Operation
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
SPT03712
Data Sheet
27
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Read A
Read B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's
Figure 7
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
SPT03713
Read Interrupted by a Read
Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0 CLK Minimum delay between the Read and Write Commands = 4 + 1 = 5 cycles DQMx t DQZ Command NOP Read A NOP NOP NOP NOP Write B NOP NOP Write latency t DQW of DQMx T1 T2 T3 T4 T5 T6 T7 T8
DQ's
DOUT A0
DIN B0
DIN B1
DIN B2
Must be Hi-Z before the Write Command "H" or "L"
SPT03787
Figure 8
Read to Write Interval
Data Sheet
28
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
(Burst Length = 4, CAS latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
DQM t DQZ
t DQW
1 Clk Interval Command NOP NOP
Bank A Activate
NOP
Read A
Write A
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's
Must be Hi-Z before the Write Command DIN A0 DIN A1 DIN A2 DIN A3
"H" or "L"
SPT03939
Figure 9
Minimum Read to Write Interval
Data Sheet
29
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
DQM t DQZ Command NOP Read A NOP NOP Read A NOP
t DQW
Write B
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's "H" or "L"
Must be Hi-Z before the Write Command DOUT A0 DOUT A1 DIN B0 DIN B1 DIN B2
DOUT A0
DIN B0
DIN B1
DIN B2
SPT03940
Figure 10
Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
NOP
Write A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQ's
DIN A0
DIN A1
DIN A2
DIN A3
don't care
The first data element and the Write are registered on the same clock edge.
Figure 11 Burst Write Operation
Extra data is ignored after termination of a Burst.
SPT03790
Data Sheet
30
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Write and Read Interrupt
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
NOP
Write A
Write B
NOP
NOP
NOP
NOP
NOP
NOP
1 Clk Interval DQ's DIN A0 DIN B0 DIN B1 DIN B2 DIN B3
SPT03791
Figure 12
Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
NOP
Write A
Read B
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's
DIN A0
don't care
DOUT B0 DOUT B1 DOUT B2 DOUT B3
DIN A0
don't care
don't care
DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from the DQ's at least one clock cycle before the Read data appears on the outputs to avoid data contention.
SPT03719
Input data for the Write is ignored.
Figure 13
Write Interrupted by a Read
Data Sheet
31
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Burst Write and Read with Auto Precharge
(Burst Length = 2, CAS latency = 2, 3 )
T0 C LK
CAS Latency = 2:
T1
T2
T3
T4
T5
T6
T7
T8
C om m and
Bank A A ctive
NOP
W rite A
Auto Precharge
NOP
NOP tWR
NOP
NOP tRP
A ctiv a te
NOP
D Q 's
CAS Latency = 3:
D IN A 0
D IN A 1
*
NOP tWR
C om m and
Bank A A ctiv e
NOP
NOP
W rite A
Auto Precharge
NOP
NOP
NOP t RP
NOP
A ctiva te
D Q 's
D IN A 0
D IN A 1
* *
B e g in A u to P re c h a rg e
B a n k ca n b e re a c tiva te d a fte r trp
SPT03909_2
Figure 14
Burst Write with Auto-Precharge
(B u rst L e n g th = 4 , C A S la te n cy = 2 , 3 )
T0 C LK T1 T2 T3 T4 T5 T6 T7 T8
C om m a nd
R e ad A w ith A P
NOP
NOP
NOP
NOP
NOP
NOP tRP
NOP
NOP
CAS la ten cy = 2 D Q 's CAS la ten cy = 3 D Q 's
*
DOUT A0 DOUT A1 DOUT A2 DOUT A3
*
DOUT A0 DOUT A1 DOUT A2
t RP
DOUT A3
* B eg in A uto P rec ha rge
B an k c an b e re ac tiv ate d after trp
S P T 0 3 72 1_ 2
Figure 15
Burst Read with Auto-Precharge
Data Sheet
32
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
AC Parameters
B u rst L e ng th = 4 , C A S L a te ncy = 2 T0 CLK t CH t CL t CK2 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 1 1 T 1 2 T 13 T 1 4 T 15 T 16 T 1 7 T 18 T 1 9 T 2 0 T 21 T 2 2
CKE t CKS t CS t CH B eg in A u to P re ch arg e B an k A B e g in A uto P re cha rge Bank B t CKH
CS
RAS
CAS
WE
BS t AH AP t AS A d d r.
RAx CAx RBx CBx RAy RAy RAz RBy RAx RBx RAy RAz RBy
DQM t RCD t RC H i-Z DQ A x0 A x1 A x2 A x3 B x0 B x1 B x2 B x3 t WR t RP t DS t DH t WR t RP t RRD
A y0 A y1 A y2 A y3
A ctivate Com m and Bank A
A ctivate Com m and Bank B W rite w ith A u to P rech a rg e Com m and Bank B
A ctiva te W rite C om m a nd C o m m an d Bank A Bank A
P re ch a rg e A ctiva te A ctiva te C o m m a nd C o m m a n d C o m m an d B a nk A Bank A Bank B
W rite w ith A uto P re cha rg e C om m an d B an k A
SPT03910_2
Figure 16
AC Parameters for a Write Timing
Data Sheet
33
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Burst Length = 2, CAS Latency = 2 T0 CLK t CH t CL CKE t CKS t CH CS RAS CAS WE BS t AH AP t AS Addr. RAx CAx t RRD t RAS DQM t AC2 t LZ t RCD DQ Hi-Z t OH t AC2 t HZ Ax1 Bx0 Bx1 t RC RBx RBx RAy RAx RBx RAy t CS t CK2 t CKH Begin Auto Precharge Bank B T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
t HZ
t RP
Ax0
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read with Auto Precharge Command Bank B
Precharge Command Bank A
Activate Command Bank A
S P T0 3 91 1 _ 2
Figure 17
AC Parameters for a Read Timing
Data Sheet
34
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
C A S La ten cy = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T 1 0 T 11 T 12 T 13 T 1 4 T 15 T 16 T 17 T 1 8 T 19 T 20 T21 T22
CLK
CKE
t RSC
CS RAS CAS WE BS AP
A ddre ss K e y
Addr.
P rec harge C o m m and A ll B ank s
A ny C o m m and
M o de R egis ter S e t C om m a nd
SPT03912_2
Figure 18
Mode Register Set
Data Sheet
35
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
T0
~ ~
T1
T2
T3
T4
T5
T6
T7
T8
~ ~
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
~ ~
CKE
High Level is required
~ ~
~ ~
Minimum of 8 Refresh Cycles are required
~ ~
2 Clock min.
CS RAS CAS WE BS AP
~ ~ ~ ~ ~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~
~ ~
~~ ~~
~~ ~~
~~ ~~
~~ ~~
Address Key
~ ~ ~~ ~~ ~~ ~~
Addr. DQM
t RP DQ
~ ~ ~ ~
~ ~
t RC
Hi-Z
Precharge Command All Banks Inputs must be stable for 200 s 1st Auto Refresh Command
8th Auto Refresh Command
Mode Register Set Command
Any Command
SPT03913
Figure 19
Power on Sequence and Auto Refresh (CBR)
Data Sheet
36
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Clock Suspension (Using CKE)
Burst Length = 4, CAS Latency = 2 T0 CLK t CK2 CKE CS RAS CAS WE BS AP Addr. DQM t CSL t CSL DQ Hi-Z Ax0 Ax1 Ax2 t CSL Ax3 t HZ
RAx RAx CAx
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Activate Read Command Command Bank A Bank A
Clock Suspend 1 Cycle
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
SPT03914
Figure 20
Clock Suspension During Burst Read CAS Latency = 2
Data Sheet
37
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Burst Length = 4, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BS AP Addr. DQM
RAx RAx CAx
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CSL
t CSL
t CSL t HZ
DQ
Hi-Z
Ax0
Ax1
Ax2
Ax3
Activate Command Bank A
Read Command Bank A
Clock Suspend 1 Cycle
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
SPT03915
Figure 21
Clock Suspension During Burst Read CAS Latency = 3
Data Sheet
38
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Burst Length = 4, CAS Latency = 2 T0 CLK t CK2 CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3
RAx RAx CAx
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Activate Command Bank A
Clock Suspend 1 Cycle Write Command Bank A
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
SPT03916
Figure 22
Clock Suspension During Burst Write CAS Latency = 2
Data Sheet
39
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Burst Length = 4, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BA A8/AP Addr. DQMx DQ Hi-Z DAx0 DAx1 DAx2 DAx3
RAx RAx CAx
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Activate Command Bank A
Clock Suspend 1 Cycle Write Command Bank A
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
SPT03917
Figure 23
Clock Suspension During Burst Write CAS Latency = 3
Data Sheet
40
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Burst Length = 4, CAS Latency = 2 T0 CLK t CK2 CKE CS RAS CAS WE BS AP Addr. DQM t HZ DQ Hi-Z Ax0 Ax1 Ax2 Ax3
RAx RAx CAx
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CKS
t CKS
Activate Command Bank A
Active Standby
Read Command Bank A
Clock Mask Start
Clock Mask End
Precharge Command Bank A
Precharge Standby
Any Command
Clock Suspend Mode Entry
Clock Suspend Mode Exit
Power Down Mode Entry
Power Down Mode Exit
SPT03918
Figure 24
Power Down Mode and Clock Suspend
Data Sheet
41
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
T0 CLK
T1
T2
T3
T4
T5 ~ ~ ~ ~
T6
T7
T8
T9
T10
T11 T12 T13 T14 T15 T16 T17 T18 T19 T20
T21 T22
CKE t CKS CS RAS CAS ~ ~ ~ ~ WE BS ~~ ~~ AP ~ ~ ~ ~ Addr. t CKS ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ tSREX DQM ~ ~ Hi-Z ~ ~ t RC
DQ
All Banks must be idle
Self Refresh Entry
Begin Self Refresh Exit Command Self Refresh Exit Command issued (async.)
Any Command
SPT03919-4
Figure 25
Self Refresh (Entry and Exit)
Data Sheet
42
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
B u rst Len gth = 4, C A S Late ncy = 2 T0 C LK t CK2 CKE T1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 1 3 T 1 4 T 1 5 T 1 6 T 17 T 18 T 19 T 20 T 21 T 22
CS
RAS
CAS
WE
BS
RAx
AP
A d dr. t RC DQM H i-Z DQ t RP (M inim um In terv al) t RC
RAx
CAx
A x 0 A x 1 A x 2 A x3
P rech arge A uto R efres h C om m and C om m a nd A ll B ank s
A uto R efres h C om m a nd
A c tiv ate C om m a nd B ank A
R e ad C om m and B a nk A
SPT03920_2
Figure 26
Auto Refresh (CBR)
Data Sheet
43
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Random Column Read (Page within same Bank)
Burst Length = 4, CAS Latency = 2 T0 CLK t CK2 CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3
RAw RAw CAw CAx CAy RAz RAz CAz
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
SPT03921
Figure 27
CAS Latency = 2
Data Sheet
44
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Burst Length = 4, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
RAw RAw CAw CAx CAy RAz RAz CAz
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A SPT03922
Figure 28
CAS Latency = 3
Data Sheet
45
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Random Column write (Page within same Bank)
B urs t L eng th = 4 , C A S L atenc y = 2 T0 C LK t CK2 CKE T1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 1 3 T 1 4 T 1 5 T 16 T 1 7 T 1 8 T 1 9 T 20 T 2 1 T 22
CS
RAS
CAS
WE
BS
AP
RBw
RBz
A d dr.
RBw
CBw
CBx
CBy
RBz
CBz
DQM Hi Z DQ
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 DBz3
A ctiva te W rite C om m an d C om m an d B a nk B B an k B
W rite W rite C o m m a nd C om m and B an k B B a nk B
P re cha rge A c tiv ate R e ad C om m and C om m and C o m m a nd B an k B B a nk B B a nk B
SPT03923_2
Figure 29
CAS Latency = 2
Data Sheet
46
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Burst Length = 4, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1
RBz RBz CBz CBx CBy RBz RBz CBz
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Activate Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B SPT03924
Figure 30
CAS Latency = 3
Data Sheet
47
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Random Row Read (Interleaving Banks) with Precharge
B u rs t Le ng th = 8 , C A S La te nc y = 2 T0 C LK t CK2 CKE H ig h T1 T2 T3 T4 T5 T6 T7 T8 T9 T1 0 T1 1 T1 2 T1 3 T1 4 T1 5 T 16 T 17 T1 8 T 19 T 20 T2 1 T2 2
CS
RAS
CAS
WE
BS
AP
RBx
RAx
RBy
A dd r.
RBx
CBx
RAx
CAx
RBy
CBy
t RCD DQM t AC2 H i-Z DQ
t RP
B x0 B x 1 B x 2 B x 3 B x 4 B x 5 B x 6 B x 7 A x0 A x 1 A x 2 A x3 A x 4 A x 5 A x 6 A x 7
B y0 By1
A c tiv a te R e ad C o m m a nd C om m an d B a nk B B an k B
A c tiva te C o m m an d B an k A
P rec ha rge A ctiv ate C o m m an d C o m m a nd B an k B B an k B R e ad C o m m a nd B a nk A
R ea d C o m m an d B an k B
SPT03925_2
Figure 31
CAS Latency = 2
Data Sheet
48
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Burst Length = 8, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BS AP Addr.
RBx RBx CBx RAx RAx CAx RBy RBy CBy
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
High
t RCD DQM DQ Hi-Z
t AC3
t RP
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Read Command Bank A
Precharge Command Bank B
Activate Command Bank B
Read Command Bank B
Precharge Command Bank A
SPT03926
Figure 32
CAS Latency = 3
Data Sheet
49
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Random Row Write (Interleaving Banks) with Precharge
B urst L en gth = 8, C A S L ate nc y = 2 T0 CLK t CK2 CKE H igh T1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 1 8 T 19 T 2 0 T 21 T 2 2
CS
RAS
CAS
WE
BS
AP
RAx
RBx
RAy
A d dr.
RAx
CAx
RBx
CBx
RAy
CAy
t RCD DQM H i-Z DQ
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7
t WR
t RP
t WR
DBx0
DBx1
DBx2
DBx3
DBx4
DBx5
DBx6
DBx7
DAy0
DAy1
DAy2
DAy3
DAy4
A c tiv ate W rite C om m a nd C o m m and B an k A B ank A
A ctiv ate W rite C om m an d C om m an d B a nk B B an k B P rec ha rge C om m and B a nk A
A ctiva te C om m an d B a nk A
P rec ha rg e C o m m a nd B an k B W rite C om m and B an k A
SPT03927_2
Figure 33
CAS Latency = 2
Data Sheet
50
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Burst Length = 8, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx RBx RBx CBx RAy RAy CAy
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
High
t RCD DQM DQ Hi-Z
t WR
t RP
t WR
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B
Precharge Command Bank A
Activate Command Bank A
Write Command Bank A
Precharge Command Bank B
SPT03928
Figure 34
CAS Latency = 3
Data Sheet
51
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Precharge termination of a Burst
Burst Length = 8 or Full Page, CAS Latency = 2 T0 CLK t CK2 CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx RAy RAy CAy RAz RAz CAz
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
High
t RP DQM
t RP
t RP
DQ
Hi Z
DAx0 DAx1 DAx2 DAx3
Ay0 Ay1 Ay2
Az0 Az1 Az2
Activate Command Bank A
Write Command Bank A Precharge Termination of a Write Burst. Write Data is masked.
Precharge Command Bank A Activate Command Bank A
Read Command Bank A
Precharge Command Bank A Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Precharge Termination of a Read Burst.
SPT03933
Figure 35
CAS Latency = 2
Data Sheet
52
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
Deep Power Down Mode
CLK CKE CS WE CAS RAS Addr. DQM DQ input DQ output High-Z
t RP
Precharge Command Deep Power Down Entry
Normal Mode
Deep Power Down Mode
DP1.vsd
Figure 36
Deep Power Down Mode Entry
Note: The deep power down mode has to be maintained for a minimum of 100s.
Data Sheet
53
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Timing Diagrams
CLK CK E CS RAS CAS WE
200 s
tRP
tRC
Deep Power Do wn exi t
All banks prec harge
Au to refresh
Auto refresh
Mode Register Set
Exte nded Mode Regis ter Set
New Com mand Accepted Here
Figure 37
Deep Power Down Exit
Note: The deep power down mode is exited by asserting CKE high. After the exit, the following sequence is needed to enter a new command: 1. 2. 3. 4. 5. Maintain NOP input conditions for a minimum of 200 s Issue precharge commands for all banks of the device Issue eight or more autorefresh commands Issue a mode register set command to initialize the mode register Issue an extended mode register set command to initialize the extende mode register
Data Sheet
54
Rev. 1.2, 04-2004
HY[B/E]25L256160AF-7.5 256MBit Mobile-RAM
Package Outline
6
Package Outline
P-TFBGA-54 (Plastic Thin Small Outline Package Type II)
tolerance 0.1mm for length and width Figure 38 Package Outline
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. SMD = Surface Mounted Device
Data Sheet 55
Dimensions in mm
Rev. 1.2, 04-2004
http://www.infineon.com
Published by Infineon Technologies AG

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